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author | Bjorn Andersson <[email protected]> | 2022-11-10 19:25:08 -0800 |
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committer | Georgi Djakov <[email protected]> | 2022-11-14 15:05:30 +0200 |
commit | 9235253ec73dfd71cc83d154693476930fc8dd77 (patch) | |
tree | 3842d2f01c1c747140230864fc214c81c62f7011 /drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | |
parent | d623264f62d40ca2d2380437f8a6318a2a9e4c66 (diff) |
interconnect: qcom: osm-l3: Add per-core EPSS L3 support
The EPSS instance in e.g. SM8350 and SC8280XP has per-core L3 voting
enabled. In this configuration, the "shared" vote is done using the
REG_L3_VOTE register instead of PERF_STATE.
Rename epss_l3 to clarify that it's affecting the PERF_STATE register
and add a new L3_VOTE description. Given platform lineage it's assumed
that the L3_VOTE-based case will be the predominant one, so use this for
a new generic qcom,epss-l3 compatible.
While adding the EPSS generic, also add qcom,osm-l3.
Signed-off-by: Bjorn Andersson <[email protected]>
Tested-by: Steev Klimaszewski <[email protected]>
Reviewed-by: Sibi Sankar <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Georgi Djakov <[email protected]>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c')
0 files changed, 0 insertions, 0 deletions