diff options
| author | Gwan-gyeong Mun <[email protected]> | 2021-07-23 10:42:37 -0700 |
|---|---|---|
| committer | Matt Roper <[email protected]> | 2021-07-29 09:32:54 -0700 |
| commit | 7711749a604996a41e14b66e3163e045a89fe8e1 (patch) | |
| tree | 1f18746b185f82e886f2398c7edbe7d401241c05 /drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c | |
| parent | a6a128116e55970a2df9f39e31e3c8373c0ff558 (diff) | |
drm/i915/dg2: Update lane disable power state during PSR
The PSR enable/disable sequences now require that we program an extra
register in the PHY to adjust the lane disable power setting.
Bspec: 49274
Bspec: 53885
Cc: Anusha Srivatsa <[email protected]>
Signed-off-by: Matt Roper <[email protected]>
Signed-off-by: Gwan-gyeong Mun <[email protected]>
Reviewed-by: Anusha Srivatsa <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c')
0 files changed, 0 insertions, 0 deletions