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| author | Charlene Liu <Charlene.Liu@amd.com> | 2022-03-10 17:20:43 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2022-03-15 14:42:01 -0400 |
| commit | a91b402d50072e4801b231925f33574f90e562ce (patch) | |
| tree | 23eea18c08f2a4248db72e2440b4b8642fd2c7f9 /drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c | |
| parent | dd15640bcee5a5fa74fc52557dd6220f48b01116 (diff) | |
drm/amd/display: Add save/restore PANEL_PWRSEQ_REF_DIV2
[why]
DCN31 has this in zstate save/restore sequence.
need for non_zstate supported ASIC
[how]
add this PANEL_PWRSEQ_REF_DIV2 to existing panel_cntl_hw_init structure.
Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Acked-by: Agustin Gutierrez <agustin.gutierrez@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c')
0 files changed, 0 insertions, 0 deletions