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| author | Andrzej Hajda <andrzej.hajda@intel.com> | 2022-12-14 08:54:39 +0100 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2022-12-30 03:04:32 -0500 |
| commit | c5bc073668206c73c20798eb6d978b5e9db5b16f (patch) | |
| tree | 8539a344e346c5a8fc836a383b23eece4fbfb153 /drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | |
| parent | 1b929c02afd37871d5afb9d498426f83432e71c2 (diff) | |
drm/i915: fix TLB invalidation for Gen12.50 video and compute engines
In case of Gen12.50 video and compute engines, TLB_INV registers are
masked - to modify one bit, corresponding bit in upper half of the register
must be enabled, otherwise nothing happens.
Fixes: 77fa9efc16a9 ("drm/i915/xehp: Create separate reg definitions for new MCR registers")
Signed-off-by: Andrzej Hajda <andrzej.hajda@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221214075439.402485-1-andrzej.hajda@intel.com
(cherry picked from commit 4d5cf7b1680a1e6db327e3c935ef58325cbedb2c)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c')
0 files changed, 0 insertions, 0 deletions