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author | Hang Yuan <hang.yuan@linux.intel.com> | 2018-09-19 14:42:10 +0800 |
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committer | Zhenyu Wang <zhenyuw@linux.intel.com> | 2018-10-31 17:08:45 +0800 |
commit | bc0686ff5fad7a842cc88377439e78be87fedc80 (patch) | |
tree | efef08ea3d043b6a88144e3f6f33749fe21408d6 /drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | |
parent | f42259ef810ce83f3e1a8ea4ce12dfda873fbe44 (diff) |
drm/i915/gvt: support inconsecutive partial gtt entry write
Previously we assumed two 4-byte writes to the same PTE coming in sequence.
But recently we observed inconsecutive partial write happening as well. So
this patch enhances the previous solution. It now uses a list to save more
partial writes. If one partial write can be combined with another one in
the list to construct a full PTE, update its shadow entry. Otherwise, save
the partial write in the list.
v2: invalidate old entry and flush ggtt (Zhenyu)
v3: split old ggtt page unmap to another patch (Zhenyu)
v4: refine codes (Zhenyu)
Signed-off-by: Hang Yuan <hang.yuan@linux.intel.com>
Cc: Yan Zhao <yan.y.zhao@intel.com>
Cc: Xiaolin Zhang <xiaolin.zhang@intel.com>
Cc: Zhenyu Wang <zhenyu.z.wang@intel.com>
Reviewed-by: Xiaolin Zhang <xiaolin.zhang@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c')
0 files changed, 0 insertions, 0 deletions