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| author | Longhe Zheng <longhe.zheng@intel.com> | 2018-10-30 16:12:10 +0800 |
|---|---|---|
| committer | Zhenyu Wang <zhenyuw@linux.intel.com> | 2018-10-31 17:09:46 +0800 |
| commit | 5e7154ff5e8e21dc9acac4f8dba7533552365374 (patch) | |
| tree | 96d36b8ca422e3aa766fb14e9556b4c845c41590 /drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c | |
| parent | 606a745944bc0ebd14f77dfc61ac7d6cb685cefe (diff) | |
drm/i915/gvt: Handle values of EDP_PSR_IMR and EDP_PSR_IIR
GVT-g only simulates DP port for guest and leaves EDP_PSR_IMR
and EDP_PSR_IIR registers as default MMIO read/write.
So guest won't get expected initial values of these registers when
initializing the gpu driver, which results in following warning and logs.
--------
Interrupt register 0x64838 is not zero: 0xffffffff
WARNING: CPU: 1 PID: 157 at drivers/gpu/drm/i915/i915_irq.c:177
gen3_assert_iir_is_zero+0x38/0xa0
Call Trace:
gen8_de_irq_postinstall+0xa7/0x400
gen8_irq_postinstall+0x27/0x80
drm_irq_install+0xbc/0x140
i915_driver_load+0xa9d/0xd50
--------
Because GVT-g does not handle EDP(embedded DP) simulation for guests,
always set EDP_PSR_IMR and EDP_PSR_IIR to value 0.
Signed-off-by: Longhe Zheng <longhe.zheng@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c')
0 files changed, 0 insertions, 0 deletions