diff options
| author | Dmitry Torokhov <[email protected]> | 2024-07-15 14:03:44 -0700 | 
|---|---|---|
| committer | Dmitry Torokhov <[email protected]> | 2024-07-15 14:03:44 -0700 | 
| commit | a23e1966932464e1c5226cb9ac4ce1d5fc10ba22 (patch) | |
| tree | bf5f1b57faa01ca31656bfc48c7d6b6f0bc39189 /drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | |
| parent | 7c7b1be19b228b450c2945ec379d7fc6bfef9852 (diff) | |
| parent | f3efefb6fdcce604413135bd8d4c5568e53a1f13 (diff) | |
Merge branch 'next' into for-linus
Prepare input updates for 6.11 merge window.
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_display.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/amdgpu_display.c | 111 | 
1 files changed, 70 insertions, 41 deletions
| diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c index b702f499f5fb..3ecc7ef95172 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_display.c @@ -38,6 +38,8 @@  #include <linux/pci.h>  #include <linux/pm_runtime.h>  #include <drm/drm_crtc_helper.h> +#include <drm/drm_damage_helper.h> +#include <drm/drm_drv.h>  #include <drm/drm_edid.h>  #include <drm/drm_fb_helper.h>  #include <drm/drm_gem_framebuffer_helper.h> @@ -124,7 +126,7 @@ static void amdgpu_display_flip_work_func(struct work_struct *__work)  	struct drm_crtc *crtc = &amdgpu_crtc->base;  	unsigned long flags; -	unsigned i; +	unsigned int i;  	int vpos, hpos;  	for (i = 0; i < work->shared_count; ++i) @@ -201,7 +203,7 @@ int amdgpu_display_crtc_page_flip_target(struct drm_crtc *crtc,  	u64 tiling_flags;  	int i, r; -	work = kzalloc(sizeof *work, GFP_KERNEL); +	work = kzalloc(sizeof(*work), GFP_KERNEL);  	if (work == NULL)  		return -ENOMEM; @@ -332,18 +334,17 @@ int amdgpu_display_crtc_set_config(struct drm_mode_set *set,  	adev = drm_to_adev(dev);  	/* if we have active crtcs and we don't have a power ref, -	   take the current one */ +	 * take the current one +	 */  	if (active && !adev->have_disp_power_ref) {  		adev->have_disp_power_ref = true;  		return ret;  	} -	/* if we have no active crtcs, then drop the power ref -	   we got before */ -	if (!active && adev->have_disp_power_ref) { -		pm_runtime_put_autosuspend(dev->dev); +	/* if we have no active crtcs, then go to +	 * drop the power ref we got before +	 */ +	if (!active && adev->have_disp_power_ref)  		adev->have_disp_power_ref = false; -	} -  out:  	/* drop the power reference we got coming in here */  	pm_runtime_put_autosuspend(dev->dev); @@ -507,11 +508,10 @@ bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector,  	if (amdgpu_connector->router.ddc_valid)  		amdgpu_i2c_router_select_ddc_port(amdgpu_connector); -	if (use_aux) { +	if (use_aux)  		ret = i2c_transfer(&amdgpu_connector->ddc_bus->aux.ddc, msgs, 2); -	} else { +	else  		ret = i2c_transfer(&amdgpu_connector->ddc_bus->adapter, msgs, 2); -	}  	if (ret != 2)  		/* Couldn't find an accessible DDC on this connector */ @@ -520,20 +520,40 @@ bool amdgpu_display_ddc_probe(struct amdgpu_connector *amdgpu_connector,  	 * EDID header starts with:  	 * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00.  	 * Only the first 6 bytes must be valid as -	 * drm_edid_block_valid() can fix the last 2 bytes */ +	 * drm_edid_block_valid() can fix the last 2 bytes +	 */  	if (drm_edid_header_is_valid(buf) < 6) {  		/* Couldn't find an accessible EDID on this -		 * connector */ +		 * connector +		 */  		return false;  	}  	return true;  } +static int amdgpu_dirtyfb(struct drm_framebuffer *fb, struct drm_file *file, +			  unsigned int flags, unsigned int color, +			  struct drm_clip_rect *clips, unsigned int num_clips) +{ + +	if (file) +		return -ENOSYS; + +	return drm_atomic_helper_dirtyfb(fb, file, flags, color, clips, +					 num_clips); +} +  static const struct drm_framebuffer_funcs amdgpu_fb_funcs = {  	.destroy = drm_gem_fb_destroy,  	.create_handle = drm_gem_fb_create_handle,  }; +static const struct drm_framebuffer_funcs amdgpu_fb_funcs_atomic = { +	.destroy = drm_gem_fb_destroy, +	.create_handle = drm_gem_fb_create_handle, +	.dirty = amdgpu_dirtyfb +}; +  uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,  					  uint64_t bo_flags)  { @@ -743,11 +763,13 @@ static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb)  			return -EINVAL;  		} -		if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(11, 0, 0)) +		if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(11, 0, 0))  			version = AMD_FMT_MOD_TILE_VER_GFX11; -		else if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) +		else if (amdgpu_ip_version(adev, GC_HWIP, 0) >= +			 IP_VERSION(10, 3, 0))  			version = AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS; -		else if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 0, 0)) +		else if (amdgpu_ip_version(adev, GC_HWIP, 0) >= +			 IP_VERSION(10, 0, 0))  			version = AMD_FMT_MOD_TILE_VER_GFX10;  		else  			version = AMD_FMT_MOD_TILE_VER_GFX9; @@ -756,13 +778,15 @@ static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb)  		case 0: /* Z microtiling */  			return -EINVAL;  		case 1: /* S microtiling */ -			if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0)) { +			if (amdgpu_ip_version(adev, GC_HWIP, 0) < +			    IP_VERSION(11, 0, 0)) {  				if (!has_xor)  					version = AMD_FMT_MOD_TILE_VER_GFX9;  			}  			break;  		case 2: -			if (adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0)) { +			if (amdgpu_ip_version(adev, GC_HWIP, 0) < +			    IP_VERSION(11, 0, 0)) {  				if (!has_xor && afb->base.format->cpp[0] != 4)  					version = AMD_FMT_MOD_TILE_VER_GFX9;  			} @@ -815,10 +839,12 @@ static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb)  			u64 render_dcc_offset;  			/* Enable constant encode on RAVEN2 and later. */ -			bool dcc_constant_encode = (adev->asic_type > CHIP_RAVEN || -						   (adev->asic_type == CHIP_RAVEN && -						    adev->external_rev_id >= 0x81)) && -						    adev->ip_versions[GC_HWIP][0] < IP_VERSION(11, 0, 0); +			bool dcc_constant_encode = +				(adev->asic_type > CHIP_RAVEN || +				 (adev->asic_type == CHIP_RAVEN && +				  adev->external_rev_id >= 0x81)) && +				amdgpu_ip_version(adev, GC_HWIP, 0) < +					IP_VERSION(11, 0, 0);  			int max_cblock_size = dcc_i64b ? AMD_FMT_MOD_DCC_BLOCK_64B :  					      dcc_i128b ? AMD_FMT_MOD_DCC_BLOCK_128B : @@ -855,7 +881,9 @@ static int convert_tiling_flags_to_modifier(struct amdgpu_framebuffer *afb)  				if (adev->family >= AMDGPU_FAMILY_NV) {  					int extra_pipe = 0; -					if ((adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) && +					if ((amdgpu_ip_version(adev, GC_HWIP, +							       0) >= +					     IP_VERSION(10, 3, 0)) &&  					    pipes == packers && pipes > 1)  						extra_pipe = 1; @@ -1136,7 +1164,11 @@ static int amdgpu_display_gem_fb_verify_and_init(struct drm_device *dev,  	if (ret)  		goto err; -	ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs); +	if (drm_drv_uses_atomic_modeset(dev)) +		ret = drm_framebuffer_init(dev, &rfb->base, +					   &amdgpu_fb_funcs_atomic); +	else +		ret = drm_framebuffer_init(dev, &rfb->base, &amdgpu_fb_funcs);  	if (ret)  		goto err; @@ -1216,8 +1248,10 @@ amdgpu_display_user_framebuffer_create(struct drm_device *dev,  	obj = drm_gem_object_lookup(file_priv, mode_cmd->handles[0]);  	if (obj ==  NULL) { -		drm_dbg_kms(dev, "No GEM object associated to handle 0x%08X, " -			    "can't create framebuffer\n", mode_cmd->handles[0]); +		drm_dbg_kms(dev, +			    "No GEM object associated to handle 0x%08X, can't create framebuffer\n", +			    mode_cmd->handles[0]); +  		return ERR_PTR(-ENOENT);  	} @@ -1316,14 +1350,6 @@ int amdgpu_display_modeset_create_props(struct amdgpu_device *adev)  					 "dither",  					 amdgpu_dither_enum_list, sz); -	if (adev->dc_enabled) { -		adev->mode_info.abm_level_property = -			drm_property_create_range(adev_to_drm(adev), 0, -						  "abm level", 0, 4); -		if (!adev->mode_info.abm_level_property) -			return -ENOMEM; -	} -  	return 0;  } @@ -1410,6 +1436,7 @@ bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc,  	}  	if (amdgpu_crtc->rmx_type != RMX_OFF) {  		fixed20_12 a, b; +  		a.full = dfixed_const(src_v);  		b.full = dfixed_const(dst_v);  		amdgpu_crtc->vsc.full = dfixed_div(a, b); @@ -1429,7 +1456,7 @@ bool amdgpu_display_crtc_scaling_mode_fixup(struct drm_crtc *crtc,   *   * \param dev Device to query.   * \param pipe Crtc to query. - * \param flags Flags from caller (DRM_CALLED_FROM_VBLIRQ or 0). + * \param flags from caller (DRM_CALLED_FROM_VBLIRQ or 0).   *              For driver internal use only also supports these flags:   *   *              USE_REAL_VBLANKSTART to use the real start of vblank instead @@ -1504,8 +1531,8 @@ int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev,  	/* Called from driver internal vblank counter query code? */  	if (flags & GET_DISTANCE_TO_VBLANKSTART) { -	    /* Caller wants distance from real vbl_start in *hpos */ -	    *hpos = *vpos - vbl_start; +		/* Caller wants distance from real vbl_start in *hpos */ +		*hpos = *vpos - vbl_start;  	}  	/* Fudge vblank to start a few scanlines earlier to handle the @@ -1527,7 +1554,7 @@ int amdgpu_display_get_crtc_scanoutpos(struct drm_device *dev,  	/* In vblank? */  	if (in_vbl) -	    ret |= DRM_SCANOUTPOS_IN_VBLANK; +		ret |= DRM_SCANOUTPOS_IN_VBLANK;  	/* Called from driver internal vblank counter query code? */  	if (flags & GET_DISTANCE_TO_VBLANKSTART) { @@ -1635,6 +1662,7 @@ int amdgpu_display_suspend_helper(struct amdgpu_device *adev)  		if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {  			struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); +  			r = amdgpu_bo_reserve(aobj, true);  			if (r == 0) {  				amdgpu_bo_unpin(aobj); @@ -1642,9 +1670,9 @@ int amdgpu_display_suspend_helper(struct amdgpu_device *adev)  			}  		} -		if (fb == NULL || fb->obj[0] == NULL) { +		if (!fb || !fb->obj[0])  			continue; -		} +  		robj = gem_to_amdgpu_bo(fb->obj[0]);  		if (!amdgpu_display_robj_is_fb(adev, robj)) {  			r = amdgpu_bo_reserve(robj, true); @@ -1671,6 +1699,7 @@ int amdgpu_display_resume_helper(struct amdgpu_device *adev)  		if (amdgpu_crtc->cursor_bo && !adev->enable_virtual_display) {  			struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo); +  			r = amdgpu_bo_reserve(aobj, true);  			if (r == 0) {  				r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM); |