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authorPeng Fan <[email protected]>2022-08-30 11:31:34 +0800
committerAbel Vesa <[email protected]>2022-09-19 13:06:45 +0300
commit0836c8604a0bfaed2396d7e2aecb4146f8c07cca (patch)
tree54657b193308a0dbf4f4ca766c8374eb1319c3fe /drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
parent2b66f02e2de174c2a9bdf60160a1d9963dc7ca2c (diff)
clk: imx: add i.MX93 clk gate
i.MX93 LPCG is different from i.MX8M CCGR. Although imx_clk_hw_gate4_flags is used here, it not strictly match i.MX93. i.MX93 has such design: - LPCG_DIRECT use BIT0 as on/off gate when LPCG_AUTHEN CPU_LPM is 0 - LPCG_LPM_CUR use BIT[2:0] as on/off gate when LPCG_AUTHEN CPU_LPM is 1 The current implementation suppose CPU_LPM is 0, and use LPCG_DIRECT BIT[1:0] as on/off gate. Although BIT1 is touched, actually BIT1 is reserved. And imx_clk_hw_gate4_flags use mask 0x3 to determine whether the clk is enabled or not, but i.MX93 LPCG only use BIT0 to control when CPU_LPM is 0. So clk disabled unused during kernel boot not able to gate off the unused clocks. To match i.MX93 LPCG, introduce imx93_clk_gate. Signed-off-by: Peng Fan <[email protected]> Reviewed-by: Ye Li <[email protected]> Reviewed-by: Jacky Bai <[email protected]> Reviewed-by: Abel Vesa <[email protected]> Signed-off-by: Abel Vesa <[email protected]> Link: https://lore.kernel.org/r/[email protected]
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_device.c')
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