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| author | Peng Fan <peng.fan@nxp.com> | 2022-08-30 11:31:33 +0800 |
|---|---|---|
| committer | Abel Vesa <abel.vesa@linaro.org> | 2022-09-19 13:06:45 +0300 |
| commit | 2b66f02e2de174c2a9bdf60160a1d9963dc7ca2c (patch) | |
| tree | 6d956a947b65635fb246cefc61b43af35cdfd30b /drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c | |
| parent | 4a3de5aa7743d1def6fba783c072e41df6b851c5 (diff) | |
clk: imx: clk-composite-93: check white_list
The CCM ROOT AUTHEN register WHITE_LIST indicate:
Each bit in this field represent for one domain. Bit16~Bit31 represent
for DOMAIN0~DOMAIN15 respectively. Only corresponding bit of the domains
is set to 1 can change the registers of this Clock Root.
i.MX93 DID is 3, so if BIT(3 + WHITE_LIST_SHIFT) is 0, the clk should be
set to read only. To make the imx93_clk_composite_flags be reusable,
add a new parameter named did(domain id);
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20220830033137.4149542-5-peng.fan@oss.nxp.com
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c')
0 files changed, 0 insertions, 0 deletions