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| author | Stanimir Varbanov <stanimir.varbanov@linaro.org> | 2022-10-05 11:37:28 +0300 |
|---|---|---|
| committer | Stanimir Varbanov <stanimir.varbanov@linaro.org> | 2022-10-25 10:31:48 +0300 |
| commit | bd32d0851c1d9879a4c792a31319b45e94ed3801 (patch) | |
| tree | f6b2e02b05e9f12a43e260a3a29006341d308ab5 /drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c | |
| parent | 15886e59cb3c04fd7705967e2905335f68446c17 (diff) | |
venus: firmware: Correct reset bit
The reset bit for A9SS reset register is BIT(4) and for XTSS_SW_RESET
it is BIT(0). Use the defines for those reset bits.
Signed-off-by: Stanimir Varbanov <stanimir.varbanov@linaro.org>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.c')
0 files changed, 0 insertions, 0 deletions