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author | Robin Chen <robin.chen@amd.com> | 2023-01-10 16:53:55 +0800 |
---|---|---|
committer | Alex Deucher <alexander.deucher@amd.com> | 2023-01-24 13:26:25 -0500 |
commit | c84ff24a77fa66aaf7c591cdf806456dcb5c2fcd (patch) | |
tree | 850012d2c09fde9c6719f0a9602ce1de9a087033 /drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | |
parent | 6ca7415f11af5200ab10bd420b513f846e9bfb99 (diff) |
drm/amd/display: Pass DSC slice height to PSR FW
[Why]
When DSC is enabled, the PSRSU seletive update region
must be multiple number of DSC slice height number.
The original solution is to overwrite the SU Y granularity
by DSC slice height in DAL driver. However, the size
of the SU Y granularity variable only has 8 bytes
and the DSC slice height may over the 8 bytes size.
[How]
Instead of overwriting the SU Y granularity value,
add a new DSC slice height pararmeter and pass it
to DMUB PSRSU FW. The PSRSU FW will refer to the
DSC slice height value and extend the SU region.
Reviewed-by: Dennis Chan <dennis.chan@amd.com>
Reviewed-by: ChunTao Tso <chuntao.tso@amd.com>
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Robin Chen <robin.chen@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c')
0 files changed, 0 insertions, 0 deletions