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authorMintz, Yuval <Yuval.Mintz@cavium.com>2017-03-23 15:50:19 +0200
committerDavid S. Miller <davem@davemloft.net>2017-03-23 11:53:30 -0700
commit810bb1f0d32e6d1d30580d4812409133ebc6fb8e (patch)
treeb8257174560c1d9ad88e780c0b05ce99ea576175 /drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
parent3981594409f3ee9ee7364d3262a22f0f1e504eee (diff)
qed: Don't waste SBs unused by RoCE
When RoCE is enabled on a given L2 interface, the interrupt lines are divided equally between L2 and RoCE - But in case number of lines needed for RoCE is limited by number of available CNQs, we can utilize the additional lines for L2. Signed-off-by: Yuval Mintz <Yuval.Mintz@cavium.com> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c')
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