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authorAlex Helms <[email protected]>2022-09-12 11:36:12 -0700
committerStephen Boyd <[email protected]>2022-09-30 17:34:20 -0700
commit09d1855656dad04127aee195baf2eedae029175d (patch)
treee3af56557df45f9fc76ac97a56cde964c2fdb3b4 /drivers/fpga/zynq-fpga.c
parent568035b01cfb107af8d2e4bd2fb9aea22cf5b868 (diff)
dt-bindings: Renesas versaclock7 device tree bindings
Renesas Versaclock7 is a family of configurable clock generator ICs with fractional and integer dividers. This driver has basic support for the RC21008A device, a clock synthesizer with a crystal input and 8 outputs. The supports changing the FOD and IOD rates, and each output can be gated. Signed-off-by: Alex Helms <[email protected]> Reviewed-by: Rob Herring <[email protected]> Link: https://lore.kernel.org/r/[email protected] Tested-by: Saeed Nowshadi <[email protected]> [[email protected]: Rename nodes in example to generic names] Signed-off-by: Stephen Boyd <[email protected]>
Diffstat (limited to 'drivers/fpga/zynq-fpga.c')
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