diff options
| author | Like Xu <[email protected]> | 2022-08-31 11:35:24 +0800 |
|---|---|---|
| committer | Peter Zijlstra <[email protected]> | 2022-09-01 11:19:42 +0200 |
| commit | f2aeea57504cbbc58da3c59b939fc16150087648 (patch) | |
| tree | c550decf5a6ea2e94397a4ba5e4d85ec7f40ab6f /drivers/fpga/xilinx-spi.c | |
| parent | 24919fdea6f8b31d7cdf32ac291bc5dd0b023878 (diff) | |
perf/x86/core: Completely disable guest PEBS via guest's global_ctrl
When a guest PEBS counter is cross-mapped by a host counter, software
will remove the corresponding bit in the arr[global_ctrl].guest and
expect hardware to perform a change of state "from enable to disable"
via the msr_slot[] switch during the vmx transaction.
The real world is that if user adjust the counter overflow value small
enough, it still opens a tiny race window for the previously PEBS-enabled
counter to write cross-mapped PEBS records into the guest's PEBS buffer,
when arr[global_ctrl].guest has been prioritised (switch_msr_special stuff)
to switch into the enabled state, while the arr[pebs_enable].guest has not.
Close this window by clearing invalid bits in the arr[global_ctrl].guest.
Fixes: 854250329c02 ("KVM: x86/pmu: Disable guest PEBS temporarily in two rare situations")
Signed-off-by: Like Xu <[email protected]>
Signed-off-by: Peter Zijlstra (Intel) <[email protected]>
Link: https://lkml.kernel.org/r/[email protected]
Diffstat (limited to 'drivers/fpga/xilinx-spi.c')
0 files changed, 0 insertions, 0 deletions