diff options
| author | Daniel Schultz <[email protected]> | 2018-03-05 13:45:11 +0100 |
|---|---|---|
| committer | Heiko Stuebner <[email protected]> | 2018-04-16 14:13:04 +0200 |
| commit | c887f5b0210c5c7d30e2da47c37798eb6f37f563 (patch) | |
| tree | 6a46ca2cf7980f49387ca334b6dce30f5b6d4409 /drivers/fpga/xilinx-spi.c | |
| parent | 5f501b42f35678615bef3f00dfb277eff1c58dfb (diff) | |
ARM: dts: rockchip: Add dp83867 CLK_OUT muxing on rk3288-phycore-som
The CLK_O_SEL default is synchronous to XI input clock, which is 25 MHz.
Set CLK_O_SEL to channel A transmit clock so we have 125 MHz on CLK_OUT.
Signed-off-by: Daniel Schultz <[email protected]>
Signed-off-by: Heiko Stuebner <[email protected]>
Diffstat (limited to 'drivers/fpga/xilinx-spi.c')
0 files changed, 0 insertions, 0 deletions