diff options
author | Maxime Ripard <[email protected]> | 2022-08-16 13:25:29 +0200 |
---|---|---|
committer | Stephen Boyd <[email protected]> | 2022-09-15 09:32:29 -0700 |
commit | af1e62f2ffe2b7fa90653f273efced0e0eabf7cc (patch) | |
tree | 6ccc75d44f7d2fb7c7563c08243fe992cde33436 /drivers/fpga/xilinx-spi.c | |
parent | 253993253466ba7187730b196174146d5247e97b (diff) |
clk: qcom: clk-rcg2: Take clock boundaries into consideration for gfx3d
The gfx3d clock is hand-crafting its own clk_rate_request in
clk_gfx3d_determine_rate to pass to the parent of that clock.
However, since the clk_rate_request is zero'd at creation, it will have
a max_rate of 0 which will break any code depending on the clock
boundaries.
That includes the recent commit 948fb0969eae ("clk: Always clamp the
rounded rate") which will clamp the rate given to clk_round_rate() to
the current clock boundaries.
For the gfx3d clock, it means that since both the min_rate and max_rate
fields are set at zero, clk_round_rate() now always return 0.
Let's initialize the min_rate and max_rate fields properly for that
clock.
Fixes: 948fb0969eae ("clk: Always clamp the rounded rate")
Signed-off-by: Maxime Ripard <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Tested-by: Linux Kernel Functional Testing <[email protected]>
Tested-by: Naresh Kamboju <[email protected]>
Signed-off-by: Stephen Boyd <[email protected]>
Diffstat (limited to 'drivers/fpga/xilinx-spi.c')
0 files changed, 0 insertions, 0 deletions