diff options
| author | Maxime Chevallier <[email protected]> | 2018-04-25 20:21:17 +0200 |
|---|---|---|
| committer | David S. Miller <[email protected]> | 2018-04-27 11:22:55 -0400 |
| commit | 9af771ced473f92b5e57d086a0c2453fc0cb149c (patch) | |
| tree | 6b07a141d39fbec6ac3908f8822a63b11179d52f /drivers/fpga/xilinx-spi.c | |
| parent | 45f972adb7f4db2d7f02af728ccd104113336074 (diff) | |
net: mvpp2: Fix clock resource by adding missing mg_core_clk
Marvell's PPv2.2 IP needs an additional clock named "MG Core clock".
This is required on Armada 7K and 8K.
This commit adds the required clock in mvpp2, making sure it's only
used on PPv2.2.
Fixes: c7e92def1ef4 ("clk: mvebu: cp110: Fix clock tree representation")
Signed-off-by: Maxime Chevallier <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
Diffstat (limited to 'drivers/fpga/xilinx-spi.c')
0 files changed, 0 insertions, 0 deletions