diff options
| author | Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com> | 2023-05-29 11:37:47 +0530 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2023-06-02 14:26:15 -0700 |
| commit | 5a3c46b809d09f8ef59e2fbf2463b1c102aecbaa (patch) | |
| tree | e5a2d9bafc6f2fdcaca7df20393f535f115add98 /drivers/fpga/xilinx-spi.c | |
| parent | f917130f19fe62c6688cc95ebebfafee3e005958 (diff) | |
drm/i915/display: Set correct voltage level for 480MHz CDCLK
According to Bspec, the voltage level for 480MHz is to be set as 1
instead of 2.
BSpec: 49208
Fixes: 06f1b06dc5b7 ("drm/i915/display: Add 480 MHz CDCLK steps for RPL-U")
v2: rebase
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230529060747.3972259-1-chaitanya.kumar.borah@intel.com
Diffstat (limited to 'drivers/fpga/xilinx-spi.c')
0 files changed, 0 insertions, 0 deletions