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authorNiklas Cassel <[email protected]>2017-12-20 00:29:37 +0100
committerLorenzo Pieralisi <[email protected]>2017-12-21 11:10:34 +0000
commit4fdd5b5b17f04fb6418a5f06adfbcf4369b8c375 (patch)
tree6619b4d50a3bf901229d23999bb1a84d862f5ab2 /drivers/fpga/xilinx-spi.c
parentb6900aeb1977ee1430578ce8b373e5c9fc6366d5 (diff)
PCI: dwc: artpec6: Deassert the core before waiting for PHY
Waiting for the PHY while the core was held in reset worked for artpec6, but for artpec7, in order to read the required registers, the core has to be out of reset. Refactor the code so we always wait for the PHY after the core has been deasserted, since this works for both artpec6 and artpec7. Signed-off-by: Niklas Cassel <[email protected]> Signed-off-by: Lorenzo Pieralisi <[email protected]>
Diffstat (limited to 'drivers/fpga/xilinx-spi.c')
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