diff options
| author | Harshit Shah <[email protected]> | 2023-12-30 14:41:23 +0530 |
|---|---|---|
| committer | Alexandre Belloni <[email protected]> | 2024-01-08 00:51:36 +0100 |
| commit | 374c13f9080a1b9835a5ed3e7bea93cf8e2dc262 (patch) | |
| tree | 49a1417ddf57be6580f63a138499331b5e4ecc43 /drivers/fpga/xilinx-pr-decoupler.c | |
| parent | 18e5794879905a788e06fb2bc40b6f5b58eae5c2 (diff) | |
i3c: master: cdns: Update maximum prescaler value for i2c clock
As per the Cadence IP document fixed the I2C clock divider value limit from
16 bits instead of 10 bits. Without this change setting up the I2C clock to
low frequencies will not work as the prescaler value might be greater than
10 bit number.
I3C clock divider value is 10 bits only. Updating the macro names for both.
Signed-off-by: Harshit Shah <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Alexandre Belloni <[email protected]>
Diffstat (limited to 'drivers/fpga/xilinx-pr-decoupler.c')
0 files changed, 0 insertions, 0 deletions