diff options
| author | Adrian Hunter <adrian.hunter@intel.com> | 2024-05-02 13:58:47 +0300 |
|---|---|---|
| committer | Ingo Molnar <mingo@kernel.org> | 2024-05-02 13:13:43 +0200 |
| commit | 9dd3612895de3d967ebd607423571bd6b0854ccc (patch) | |
| tree | 5610b3be0b1ce7957e0f53e88486b45c60418284 /drivers/fpga/xilinx-core.c | |
| parent | b8000264348979b60dbe479255570a40e1b3a097 (diff) | |
x86/insn: Add misc new Intel instructions
The x86 instruction decoder is used not only for decoding kernel
instructions. It is also used by perf uprobes (user space probes) and by
perf tools Intel Processor Trace decoding. Consequently, it needs to
support instructions executed by user space also.
Add instructions documented in Intel Architecture Instruction Set
Extensions and Future Features Programming Reference March 2024
319433-052, that have not been added yet:
AADD
AAND
AOR
AXOR
CMPccXADD
PBNDKB
RDMSRLIST
URDMSR
UWRMSR
VBCSTNEBF162PS
VBCSTNESH2PS
VCVTNEEBF162PS
VCVTNEEPH2PS
VCVTNEOBF162PS
VCVTNEOPH2PS
VCVTNEPS2BF16
VPDPB[SU,UU,SS]D[,S]
VPDPW[SU,US,UU]D[,S]
VPMADD52HUQ
VPMADD52LUQ
VSHA512MSG1
VSHA512MSG2
VSHA512RNDS2
VSM3MSG1
VSM3MSG2
VSM3RNDS2
VSM4KEY4
VSM4RNDS4
WRMSRLIST
TCMMIMFP16PS
TCMMRLFP16PS
TDPFP16PS
PREFETCHIT1
PREFETCHIT0
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Link: https://lore.kernel.org/r/20240502105853.5338-5-adrian.hunter@intel.com
Diffstat (limited to 'drivers/fpga/xilinx-core.c')
0 files changed, 0 insertions, 0 deletions