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| author | André Draszik <[email protected]> | 2024-06-17 17:44:45 +0100 |
|---|---|---|
| committer | Vinod Koul <[email protected]> | 2024-07-02 18:52:05 +0530 |
| commit | 26ba3261215b44d466bd2093daf3796031c09c0a (patch) | |
| tree | 412aef6651a9427777b906f6b80f6ff6e58d62ab /drivers/fpga/xilinx-core.c | |
| parent | 54290bd9811ecdd82c19b96093e2c78325f59574 (diff) | |
phy: exynos5-usbdrd: convert (phy) register access clock to clk_bulk
In preparation for support for additional platforms, convert the phy
register access clock to using the clk_bulk interfaces.
Newer SoCs like Google Tensor gs101 require additional clocks for
access to additional (different) register areas (PHY, PMA, PCS), and
converting to clk_bulk simplifies addition of those extra clocks.
Signed-off-by: André Draszik <[email protected]>
Reviewed-by: Peter Griffin <[email protected]>
Tested-by: Peter Griffin <[email protected]>
Tested-by: Will McVicker <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Vinod Koul <[email protected]>
Diffstat (limited to 'drivers/fpga/xilinx-core.c')
0 files changed, 0 insertions, 0 deletions