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| author | Bhargava Chenna Marreddy <bhargava.marreddy@broadcom.com> | 2024-10-08 00:41:41 -0700 |
|---|---|---|
| committer | Jason Gunthorpe <jgg@nvidia.com> | 2024-10-11 20:49:02 -0300 |
| commit | 7988bdbbb85ac85a847baf09879edcd0f70521dc (patch) | |
| tree | 9abfbb7aa781cd9c978adad5b62e4e121b44c7fe /drivers/fpga/tests/fpga-region-test.c | |
| parent | 2df411353dacc4b0c911f8c4944f8ffab955391c (diff) | |
RDMA/bnxt_re: Fix a bug while setting up Level-2 PBL pages
Avoid memory corruption while setting up Level-2 PBL pages for the non MR
resources when num_pages > 256K.
There will be a single PDE page address (contiguous pages in the case of >
PAGE_SIZE), but, current logic assumes multiple pages, leading to invalid
memory access after 256K PBL entries in the PDE.
Fixes: 0c4dcd602817 ("RDMA/bnxt_re: Refactor hardware queue memory allocation")
Link: https://patch.msgid.link/r/1728373302-19530-10-git-send-email-selvin.xavier@broadcom.com
Signed-off-by: Bhargava Chenna Marreddy <bhargava.marreddy@broadcom.com>
Signed-off-by: Selvin Xavier <selvin.xavier@broadcom.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Diffstat (limited to 'drivers/fpga/tests/fpga-region-test.c')
0 files changed, 0 insertions, 0 deletions