diff options
| author | Yang Xiwen <[email protected]> | 2024-02-19 23:05:28 +0800 |
|---|---|---|
| committer | Krzysztof Kozlowski <[email protected]> | 2024-04-08 09:29:36 +0200 |
| commit | c7a3ad884d1dc1302dcc3295baa18917180b8bec (patch) | |
| tree | 8af7a0d7ab5ac68d9317ab318ad8951857837012 /drivers/fpga/tests/fpga-bridge-test.c | |
| parent | f00a6b9644a5668e25ad9ca5aff53b6de4b0aaf6 (diff) | |
arm64: dts: hi3798cv200: add cache info
During boot, the kernel complains:
[ 0.044029] cacheinfo: Unable to detect cache hierarchy for CPU 0
So add L1/L2 cache info to the dts according to the datasheet. (32KiB L1
i-cache + 32 KiB L1 d-cache + 512 KiB L2 unified cache)
With this patch, the line above is gone and the following info is added
to the output of `lscpu`:
Caches (sum of all):
L1d: 128 KiB (4 instances)
L1i: 128 KiB (4 instances)
L2: 512 KiB (1 instance)
Signed-off-by: Yang Xiwen <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
[krzysztof: drop Fixes/cc-stable, because this is a missing feature, not
a fix]
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Diffstat (limited to 'drivers/fpga/tests/fpga-bridge-test.c')
0 files changed, 0 insertions, 0 deletions