diff options
| author | Christoph Niedermaier <[email protected]> | 2021-12-08 16:05:43 +0100 |
|---|---|---|
| committer | Shawn Guo <[email protected]> | 2021-12-14 16:29:23 +0800 |
| commit | e7ed6ba0239df1e2aca3f9b2d77da4de180cdbe0 (patch) | |
| tree | a2a4d7698cbabf95e5e91dd4adbaf60c7a94ed9e /drivers/fpga/machxo2-spi.c | |
| parent | bca46d8e5fede9cf4491be27dba9d09721b80f71 (diff) | |
ARM: dts: imx6qdl-dhcom: Align PHY reset timing with other DHCOM SoMs
According to datasheet Microchip LAN8710A/LAN8710Ai DS00002164B [1]
the reset should stay asserted for at least 100uS and software
should wait at least 200nS. On other DHCOM SoMs with the SMSC
LAN8710Ai PHY both reset delays are 500us. This should be plenty
and for consistency, the i.MX6 SoM should also use these delays.
[1] https://ww1.microchip.com/downloads/en/DeviceDoc/00002164B.pdf
Signed-off-by: Christoph Niedermaier <[email protected]>
Cc: Shawn Guo <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Marek Vasut <[email protected]>
Cc: NXP Linux Team <[email protected]>
Cc: [email protected]
To: [email protected]
Reviewed-by: Fabio Estevam <[email protected]>
Signed-off-by: Shawn Guo <[email protected]>
Diffstat (limited to 'drivers/fpga/machxo2-spi.c')
0 files changed, 0 insertions, 0 deletions