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| author | Like Xu <[email protected]> | 2021-08-02 15:08:50 +0800 |
|---|---|---|
| committer | Peter Zijlstra <[email protected]> | 2021-08-04 15:16:34 +0200 |
| commit | df51fe7ea1c1c2c3bfdb81279712fdd2e4ea6c27 (patch) | |
| tree | a9c39906aad73f1a0132460c6decb5a274b32e30 /drivers/fpga/machxo2-spi.c | |
| parent | f4b4b45652578357031fbbef7f7a1b04f6fa2dc3 (diff) | |
perf/x86/amd: Don't touch the AMD64_EVENTSEL_HOSTONLY bit inside the guest
If we use "perf record" in an AMD Milan guest, dmesg reports a #GP
warning from an unchecked MSR access error on MSR_F15H_PERF_CTLx:
[] unchecked MSR access error: WRMSR to 0xc0010200 (tried to write 0x0000020000110076) at rIP: 0xffffffff8106ddb4 (native_write_msr+0x4/0x20)
[] Call Trace:
[] amd_pmu_disable_event+0x22/0x90
[] x86_pmu_stop+0x4c/0xa0
[] x86_pmu_del+0x3a/0x140
The AMD64_EVENTSEL_HOSTONLY bit is defined and used on the host,
while the guest perf driver should avoid such use.
Fixes: 1018faa6cf23 ("perf/x86/kvm: Fix Host-Only/Guest-Only counting with SVM disabled")
Signed-off-by: Like Xu <[email protected]>
Signed-off-by: Peter Zijlstra (Intel) <[email protected]>
Reviewed-by: Liam Merwick <[email protected]>
Tested-by: Kim Phillips <[email protected]>
Tested-by: Liam Merwick <[email protected]>
Link: https://lkml.kernel.org/r/[email protected]
Diffstat (limited to 'drivers/fpga/machxo2-spi.c')
0 files changed, 0 insertions, 0 deletions