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author | Dan Williams <[email protected]> | 2022-06-01 12:49:32 -0700 |
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committer | Dan Williams <[email protected]> | 2022-07-10 12:10:07 -0700 |
commit | ee800010835db23c70acc01000f182955cab27a5 (patch) | |
tree | bb7678bc2cd22ea26b50b23f772d1124de3e61d9 /drivers/fpga/fpga-mgr.c | |
parent | 08f8d040a11d539481b9aee7b482430561281a28 (diff) |
cxl/port: Cache CXL host bridge data
Region creation has need for checking host-bridge connectivity when
adding endpoints to regions. Record, at port creation time, the
host-bridge to provide a useful shortcut from any location in the
topology to the most-significant ancestor.
Reviewed-by: Jonathan Cameron <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Dan Williams <[email protected]>
Diffstat (limited to 'drivers/fpga/fpga-mgr.c')
0 files changed, 0 insertions, 0 deletions