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author | Dan Williams <[email protected]> | 2022-07-21 17:19:12 -0700 |
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committer | Dan Williams <[email protected]> | 2022-07-21 17:19:12 -0700 |
commit | 9c57cde0dcbd0f76f649d152b83a2b9316277b22 (patch) | |
tree | fbf5ec6bdf1925018dd50d2c67e2f6d0a8c727b1 /drivers/fpga/fpga-mgr.c | |
parent | 3bf65915cefa879e3693a824d8801a08e4778619 (diff) |
cxl/hdm: Enumerate allocated DPA
In preparation for provisioning CXL regions, add accounting for the DPA
space consumed by existing regions / decoders. Recall, a CXL region is a
memory range comprised from one or more endpoint devices contributing a
mapping of their DPA into HPA space through a decoder.
Record the DPA ranges covered by committed decoders at initial probe of
endpoint ports relative to a per-device resource tree of the DPA type
(pmem or volatile-ram).
The cxl_dpa_rwsem semaphore is introduced to globally synchronize DPA
state across all endpoints and their decoders at once. The vast majority
of DPA operations are reads as region creation is expected to be as rare
as disk partitioning and volume creation. The device_lock() for this
synchronization is specifically avoided for concern of entangling with
sysfs attribute removal.
Co-developed-by: Ben Widawsky <[email protected]>
Signed-off-by: Ben Widawsky <[email protected]>
Reviewed-by: Jonathan Cameron <[email protected]>
Link: https://lore.kernel.org/r/165784327682.1758207.7914919426043855876.stgit@dwillia2-xfh.jf.intel.com
Signed-off-by: Dan Williams <[email protected]>
Diffstat (limited to 'drivers/fpga/fpga-mgr.c')
0 files changed, 0 insertions, 0 deletions