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author | Dan Williams <[email protected]> | 2022-06-07 10:35:39 -0700 |
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committer | Dan Williams <[email protected]> | 2022-07-21 17:19:25 -0700 |
commit | 7f8faf96a2fb562833db73595640329ca8da7b1d (patch) | |
tree | aa1d56a296dd10cf81a951324fe07594e9773722 /drivers/fpga/fpga-mgr.c | |
parent | 538831f1beb818c93e5879bf19de37d89ec88ed6 (diff) |
cxl/mem: Enumerate port targets before adding endpoints
The port scanning algorithm in devm_cxl_enumerate_ports() walks up the
topology and adds cxl_port objects starting from the root down to the
endpoint. When those ports are initially created they know all their
dports, but they do not know the downstream cxl_port instance that
represents the next descendant in the topology. Rework create_endpoint()
into devm_cxl_add_endpoint() that enumerates the downstream cxl_port
topology into each port's 'struct cxl_ep' record for each endpoint it
that the port is an ancestor.
Reviewed-by: Jonathan Cameron <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Dan Williams <[email protected]>
Diffstat (limited to 'drivers/fpga/fpga-mgr.c')
0 files changed, 0 insertions, 0 deletions