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authorAngeloGioacchino Del Regno <[email protected]>2023-05-16 15:52:05 +0200
committerStephen Boyd <[email protected]>2023-06-12 18:20:04 -0700
commitf235f6ae59e5060af6d924038348f94a6348ee8d (patch)
tree1b285646e19ac33b18fb003f39f29aebadec6efc /drivers/fpga/fpga-bridge.c
parent1775790eff4a8fa885db189c75f4ce98e7a6a1dc (diff)
clk: mediatek: Remove CLK_SET_PARENT from all MSDC core clocks
Various MSDC core clocks, used for multiple MSDC controller instances, share the same parent(s): in order to add parents selection in the mtk-sd driver to achieve an accurate clock rate for all modes, remove the CLK_SET_RATE_PARENT flag from all MSDC clocks for all SoCs: this will make sure that a clk_set_rate() call performed for a clock on a secondary controller will not change the rate of a common parent, which would result in an overclock or underclock of one of the controllers. Signed-off-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: Matthias Brugger <[email protected]> Reviewed-by: Markus Schneider-Pargmann <[email protected]> Link: https://lore.kernel.org/r/[email protected] Tested-by: Alexandre Mergnat <[email protected]> Reviewed-by: Alexandre Mergnat <[email protected]> Signed-off-by: Stephen Boyd <[email protected]>
Diffstat (limited to 'drivers/fpga/fpga-bridge.c')
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