diff options
| author | Masahiro Yamada <[email protected]> | 2018-04-12 11:16:10 +0900 |
|---|---|---|
| committer | Philipp Zabel <[email protected]> | 2018-04-27 11:51:12 +0200 |
| commit | e6914365fd280fce303a89b8a8d4529af5a2e0f9 (patch) | |
| tree | 7d312144a03808209b8f67aa4bc24d3da3d7466e /drivers/fpga/fpga-bridge.c | |
| parent | 60cc43fc888428bb2f18f08997432d426a243338 (diff) | |
reset: uniphier: fix USB clock line for LD20
For LD20, the bit 5 of the offset 0x200c turned out to be a USB3
reset. The hardware document says it is the GIO reset despite LD20
has no GIO bus, confusingly.
Also, fix confusing comments for PXs3.
Signed-off-by: Masahiro Yamada <[email protected]>
Signed-off-by: Philipp Zabel <[email protected]>
Diffstat (limited to 'drivers/fpga/fpga-bridge.c')
0 files changed, 0 insertions, 0 deletions