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authorSergio Paracuellos <[email protected]>2023-06-19 06:09:36 +0200
committerThomas Bogendoerfer <[email protected]>2023-06-21 14:50:22 +0200
commitdaf73c70f69386fb15960526772ef584a4efcaf2 (patch)
treeb7effe82a66cd810437f4c57717c2163b0513228 /drivers/fpga/fpga-bridge.c
parentffcdf47379eae86dc8f8f02c62994dacf2c9038e (diff)
mips: ralink: rt305x: remove clock related code
A properly clock driver for ralink SoCs has been added. Hence there is no need to have clock related code in 'arch/mips/ralink' folder anymore. Signed-off-by: Sergio Paracuellos <[email protected]> Signed-off-by: Thomas Bogendoerfer <[email protected]>
Diffstat (limited to 'drivers/fpga/fpga-bridge.c')
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