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authorLuca Ceresoli <[email protected]>2022-04-21 23:32:51 +0200
committerMark Brown <[email protected]>2022-04-25 14:01:01 +0100
commitd5d933f09ac326aebad85bfb787cc786ad477711 (patch)
tree5540847d65f8467d2a8d741dea18b4bcecba33bb /drivers/fpga/fpga-bridge.c
parent40b6a137717bb5ca5ccb4e4b051e0d22019cd188 (diff)
spi: rockchip: fix missing error on unsupported SPI_CS_HIGH
The hardware (except for the ROCKCHIP_SPI_VER2_TYPE2 version) does not support active-high native chip selects. However if such a CS is configured the core does not error as it normally should, because the 'ctlr->use_gpio_descriptors = true' line in rockchip_spi_probe() makes the core set SPI_CS_HIGH in ctlr->mode_bits. In such a case the spi-rockchip driver operates normally but produces an active-low chip select signal without notice. There is no provision in the current core code to handle this situation. Fix by adding a check in the ctlr->setup function (similarly to what spi-atmel.c does). This cannot be done reading the SPI_CS_HIGH but in ctlr->mode_bits because that bit gets always set by the core for master mode (see above). Fixes: eb1262e3cc8b ("spi: spi-rockchip: use num-cs property and ctlr->enable_gpiods") Signed-off-by: Luca Ceresoli <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mark Brown <[email protected]>
Diffstat (limited to 'drivers/fpga/fpga-bridge.c')
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