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authorTianyang Zhang <[email protected]>2024-08-23 18:43:36 +0800
committerThomas Gleixner <[email protected]>2024-08-23 20:40:27 +0200
commita1d4646d34c6642194a421ca9afbd060b0f9aa00 (patch)
tree0c43161aacc1759f33e08c33769f3c1203865d44 /drivers/fpga/fpga-bridge.c
parent9e83dd3ebb14fadccb936308b7b101c75da76324 (diff)
irqchip/loongson-pch-msi: Prepare get_pch_msi_handle() for AVECINTC
On Loongson-3C6000 and higher systems with AVECINTC irqchip, there may be multiple PCI segments, but only one PCH-MSI irq domain. In this case, let get_pch_msi_handle() return the first domain handle. Co-developed-by: Jianmin Lv <[email protected]> Signed-off-by: Jianmin Lv <[email protected]> Co-developed-by: Liupu Wang <[email protected]> Signed-off-by: Liupu Wang <[email protected]> Co-developed-by: Huacai Chen <[email protected]> Signed-off-by: Huacai Chen <[email protected]> Signed-off-by: Tianyang Zhang <[email protected]> Signed-off-by: Thomas Gleixner <[email protected]> Link: https://lore.kernel.org/all/[email protected]
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