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authorNiklas Söderlund <[email protected]>2023-02-11 15:36:53 +0100
committerGeert Uytterhoeven <[email protected]>2023-03-06 10:42:14 +0100
commit8b406fd422d568a407a98c2809c0b2c6bdc95be3 (patch)
tree2c986a217a3ae218ce116768e04f88c81f22cf77 /drivers/fpga/fpga-bridge.c
parent7502a04dae0e614bc14553e31461e50499bc67aa (diff)
clk: renesas: r8a779g0: Add CSI-2 clocks
Add the CSI core clock and the CSI40 and CSI41 module clocks, which are used by the CSI-2 Interfaces on the Renesas R-Car V4H (R8A779G0) SoC. Signed-off-by: Niklas Söderlund <[email protected]> Reviewed-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
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