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| author | Michael Walle <[email protected]> | 2024-07-30 21:49:05 +0200 |
|---|---|---|
| committer | Alexandre Belloni <[email protected]> | 2024-09-12 00:33:33 +0200 |
| commit | 80bf13c07c07c43cc959b253305b64922cb20a92 (patch) | |
| tree | 987108e72fd0a4d1ab06f6c7d16013c0058b1cf2 /drivers/fpga/fpga-bridge.c | |
| parent | 0cfd26cc06ff353e9b59d0ee57a4950df2abd616 (diff) | |
rtc: sun6i: disable automatic clock input switching
The V3(s) will detect a valid external low frequency clock and if it is
not present will automatically switch to the internal one. This might
hide bugs and (hardware) configuration errors. It's even worse because
the internal RTC runs significantly slower (32.000Hz vs 32.768Hz).
Fortunately for us, the V3(s) has an (undocumented) bypass of this
switching and the driver already supports it by setting the
.has_auto_swt flag.
Signed-off-by: Michael Walle <[email protected]>
Acked-by: Chen-Yu Tsai <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Alexandre Belloni <[email protected]>
Diffstat (limited to 'drivers/fpga/fpga-bridge.c')
0 files changed, 0 insertions, 0 deletions