diff options
| author | William Breathitt Gray <[email protected]> | 2023-04-06 10:40:15 -0400 |
|---|---|---|
| committer | Jonathan Cameron <[email protected]> | 2023-04-10 12:26:34 +0100 |
| commit | 7c95a3f51a54db694d3eeef60e77e3a8558ef25e (patch) | |
| tree | 95d5ffa2c3e272de0eaf10ab94d4b9f295c91129 /drivers/fpga/fpga-bridge.c | |
| parent | c7301b848191f18719c5a6247300998269059c0b (diff) | |
iio: addac: stx104: Use regmap_read_poll_timeout() for conversion poll
ADC sample captures take a certain amount of time to complete after
initiated; this conversion time range can be anywhere from 5
microseconds to 53.68 seconds depending on the configuration of the
Analog Input Frame Timer register. When the conversion is in progress,
the ADC Status register CNV bit is high. Call regmap_read_poll_timeout()
to poll until the ADC conversion is completed (or timeout if more than
53.68 seconds passes).
Suggested-by: Jonathan Cameron <[email protected]>
Signed-off-by: William Breathitt Gray <[email protected]>
Link: https://lore.kernel.org/r/9ef433f107afd1d4dcd2d97ef0e932d7045c2bbd.1680790580.git.william.gray@linaro.org
Signed-off-by: Jonathan Cameron <[email protected]>
Diffstat (limited to 'drivers/fpga/fpga-bridge.c')
0 files changed, 0 insertions, 0 deletions