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authorThéo Lebrun <[email protected]>2024-11-06 17:03:57 +0100
committerStephen Boyd <[email protected]>2024-11-14 14:52:27 -0800
commit5e01124a2c0a42dc6b587b0b09b204a5389f8d7b (patch)
tree54c61b8bd75f848cccc5d19d753d66ca0a61cd22 /drivers/fpga/fpga-bridge.c
parent4a1ae0486dfee0aa3dcf3d312ece326870341f57 (diff)
clk: eyeq: add EyeQ5 fixed factor clocks
Expose additional clocks on EyeQ5. Some indexes come from dt-bindings headers, others are private to the driver. Few clocks are early (of_clk_init() stage: core clocks and UART clock), others can wait until platform device probe. The source for this list is downstream Mobileye kernel and some internal documentation. Signed-off-by: Théo Lebrun <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
Diffstat (limited to 'drivers/fpga/fpga-bridge.c')
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