diff options
author | Yanfei Xu <[email protected]> | 2024-08-28 16:42:28 +0800 |
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committer | Dave Jiang <[email protected]> | 2024-09-09 11:33:44 -0700 |
commit | 55e268694e8b07026c88191f9b6949b6887d9ce3 (patch) | |
tree | 1efbb09471ea0660edd7d4b756120241247c2705 /drivers/fpga/fpga-bridge.c | |
parent | d75ccd4f2ea2aa2679e6c807d76953dcd3f9d56d (diff) |
cxl/pci: Fix to record only non-zero ranges
The function cxl_dvsec_rr_decode() retrieves and records DVSEC ranges
into info->dvsec_range[], regardless of whether it is non-zero range,
and the variable info->ranges indicates the number of non-zero ranges.
However, in cxl_hdm_decode_init(), the validation for
info->dvsec_range[] occurs in a for loop that iterates based on
info->ranges. It may result in zero range to be validated but non-zero
range not be validated, in turn, the number of allowed ranges is to be
0. Address it by only record non-zero ranges.
This fix is not urgent as it requires a configuration that zeroes out
the first dvsec range while populating the second. This has not been
observed, but it is theoretically possible. If this gets picked up for
-stable, no harm done, but there is no urgency to backport.
Fixes: 560f78559006 ("cxl/pci: Retrieve CXL DVSEC memory info")
Reviewed-by: Jonathan Cameron <[email protected]>
Signed-off-by: Yanfei Xu <[email protected]>
Reviewed-by: Alison Schofield <[email protected]>
Link: https://patch.msgid.link/[email protected]
Signed-off-by: Dave Jiang <[email protected]>
Diffstat (limited to 'drivers/fpga/fpga-bridge.c')
0 files changed, 0 insertions, 0 deletions