diff options
| author | Claudiu Beznea <[email protected]> | 2024-10-19 11:47:27 +0300 |
|---|---|---|
| committer | Geert Uytterhoeven <[email protected]> | 2024-10-25 10:54:21 +0200 |
| commit | 49991cca67d584a59cb10d48825cce3d11f7d843 (patch) | |
| tree | 33250834b911caf696f3c07b9e02c52a38a9c286 /drivers/fpga/fpga-bridge.c | |
| parent | 9852d85ec9d492ebef56dc5f229416c925758edc (diff) | |
dt-bindings: clock: r9a08g045-cpg: Add power domain ID for RTC
The RTC and VBATTB don't share the MSTOP control bit (but only the bus
clock and the reset signal). As the MSTOP control is modeled though power
domains add power domain ID for the RTC device available on the
Renesas RZ/G3S SoC.
Signed-off-by: Claudiu Beznea <[email protected]>
Acked-by: Krzysztof Kozlowski <[email protected]>
Reviewed-by: Geert Uytterhoeven <[email protected]>
Link: https://lore.kernel.org/[email protected]
Signed-off-by: Geert Uytterhoeven <[email protected]>
Diffstat (limited to 'drivers/fpga/fpga-bridge.c')
0 files changed, 0 insertions, 0 deletions