bpf, riscv: Enable zext optimization for more RV64G ALU ops

Commit 66d0d5a854a6 ("riscv: bpf: eliminate zero extension code-gen")
added the new zero-extension optimization for some BPF ALU operations.

Since then, bugs in the JIT that have been fixed in the bpf tree require
this optimization to be added to other operations: commit 1e692f09e091
("bpf, riscv: clear high 32 bits for ALU32 add/sub/neg/lsh/rsh/arsh"),
and commit fe121ee531d1 ("bpf, riscv: clear target register high 32-bits
for and/or/xor on ALU32").

Now that these have been merged to bpf-next, the zext optimization can
be enabled for the fixed operations.

Signed-off-by: Luke Nelson <[email protected]>
Cc: Song Liu <[email protected]>
Cc: Jiong Wang <[email protected]>
Cc: Xi Wang <[email protected]>
Acked-by: Björn Töpel <[email protected]>
Acked-by: Jiong Wang <[email protected]>
Signed-off-by: Daniel Borkmann <[email protected]>

0 files changed, 0 insertions, 0 deletions