diff options
| author | Anthony Koo <[email protected]> | 2019-02-08 20:50:51 -0500 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2019-03-19 15:04:03 -0500 |
| commit | 46570f090469c8c453622523ae5ccede256148f5 (patch) | |
| tree | 33c35caefc477e64a00e03fb8efd287b6473bbdd /drivers/fpga/fpga-bridge.c | |
| parent | f5031000603fc528034abe208230dbc6a733a95b (diff) | |
drm/amd/display: Keep clocks high before seamless boot done
[Why]
UEFI boot usually uses a boot profile that uses higher clocks
and watermark settings.
UEFI boot surface is less optimal, for example it uses linear surface
[How]
Before we finish our seamless boot sequence, keep the clock and
watermark settings from boot.
Update to optimal settings only after first flip away from UEFI
frame buffer.
Signed-off-by: Anthony Koo <[email protected]>
Reviewed-by: Aric Cyr <[email protected]>
Acked-by: Bhawanpreet Lakha <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'drivers/fpga/fpga-bridge.c')
0 files changed, 0 insertions, 0 deletions