diff options
| author | Guiting Shen <[email protected]> | 2023-08-13 20:55:20 +0800 |
|---|---|---|
| committer | Mark Brown <[email protected]> | 2023-08-14 13:10:37 +0100 |
| commit | 11e756cc85fac43e2025306ad6aea80114cc7e98 (patch) | |
| tree | 0de0b0fd6803b8f20adc4fee815a6d2e97e9b148 /drivers/fpga/fpga-bridge.c | |
| parent | b39eee2754e9fbcbbdd866c1aad59575d8c4342e (diff) | |
ASoC: tlv320aic32x4: Fix the divide by zero
The value of register(NDAC,MDAC,NADC,MADC,BCLKN) maybe zero lead to
divide by zero in clk_aic32x4_div_recalc_rate().And the rate should be
divide by 128 if the value was zero in this function according to the
datasheet.
Add the macro AIC32X4_DIV_MAX to present the 128 and return 0 if failing
to read the value of register.
Signed-off-by: Guiting Shen <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Mark Brown <[email protected]>
Diffstat (limited to 'drivers/fpga/fpga-bridge.c')
0 files changed, 0 insertions, 0 deletions