diff options
| author | Robert Hancock <[email protected]> | 2022-03-04 20:24:43 -0600 |
|---|---|---|
| committer | David S. Miller <[email protected]> | 2022-03-05 11:12:08 +0000 |
| commit | 0b79b8dc97b9df4f873f63161e3050bafc4c4237 (patch) | |
| tree | fbbf0f36b2bc8ab8cd7b3c6096e662665566d7c7 /drivers/fpga/fpga-bridge.c | |
| parent | 40da5d680e02ca8d61237192db4b5833d3c9639f (diff) | |
net: axienet: add coalesce timer ethtool configuration
Add the ability to configure the RX/TX coalesce timer with ethtool.
Change default setting to scale with the clock rate rather than being a
fixed number of clock cycles.
Signed-off-by: Robert Hancock <[email protected]>
Signed-off-by: David S. Miller <[email protected]>
Diffstat (limited to 'drivers/fpga/fpga-bridge.c')
0 files changed, 0 insertions, 0 deletions