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| author | Jagan Teki <jagan@amarulasolutions.com> | 2018-09-04 12:40:49 +0800 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@bootlin.com> | 2018-09-05 09:19:59 +0200 |
| commit | 8b2a37870419f4aa6e6f837aa8ec627eae984010 (patch) | |
| tree | 77d847f9e300a112d543d25d9af1a02f0b1d7c2a /drivers/fpga/altera-fpga2sdram.c | |
| parent | 5de39acaf34604bd04834f092479cf4dcc946dd4 (diff) | |
dt-bindings: clock: sun50i-a64-ccu: Add PLL_VIDEO0 macro
Allwinner A64 HDMI PHY clock has PLL_VIDEO0 as a parent.
Include the macro on dt-bindings so-that the same can be used
while defining CCU clock phandles.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
Diffstat (limited to 'drivers/fpga/altera-fpga2sdram.c')
0 files changed, 0 insertions, 0 deletions