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authorIngo Molnar <[email protected]>2018-10-09 08:50:10 +0200
committerIngo Molnar <[email protected]>2018-10-09 08:50:10 +0200
commitfc8eaa85681fa72dc6a4e46f01c92e4fba83d0ab (patch)
treeb044fab426f2167ceeb37ed6fe58f7f11b10cebd /drivers/clocksource/timer-fttmr010.c
parent2cc81c6992248ea37d0241bc325977bab310bc3b (diff)
parent49e00eee00612b1357596fed8a88b621a7648c14 (diff)
Merge branch 'x86/urgent' into x86/cache, to pick up dependent fix
Signed-off-by: Ingo Molnar <[email protected]>
Diffstat (limited to 'drivers/clocksource/timer-fttmr010.c')
-rw-r--r--drivers/clocksource/timer-fttmr010.c18
1 files changed, 11 insertions, 7 deletions
diff --git a/drivers/clocksource/timer-fttmr010.c b/drivers/clocksource/timer-fttmr010.c
index c020038ebfab..cf93f6419b51 100644
--- a/drivers/clocksource/timer-fttmr010.c
+++ b/drivers/clocksource/timer-fttmr010.c
@@ -130,13 +130,17 @@ static int fttmr010_timer_set_next_event(unsigned long cycles,
cr &= ~fttmr010->t1_enable_val;
writel(cr, fttmr010->base + TIMER_CR);
- /* Setup the match register forward/backward in time */
- cr = readl(fttmr010->base + TIMER1_COUNT);
- if (fttmr010->count_down)
- cr -= cycles;
- else
- cr += cycles;
- writel(cr, fttmr010->base + TIMER1_MATCH1);
+ if (fttmr010->count_down) {
+ /*
+ * ASPEED Timer Controller will load TIMER1_LOAD register
+ * into TIMER1_COUNT register when the timer is re-enabled.
+ */
+ writel(cycles, fttmr010->base + TIMER1_LOAD);
+ } else {
+ /* Setup the match register forward in time */
+ cr = readl(fttmr010->base + TIMER1_COUNT);
+ writel(cr + cycles, fttmr010->base + TIMER1_MATCH1);
+ }
/* Start */
cr = readl(fttmr010->base + TIMER_CR);