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authorAtish Patra <[email protected]>2018-10-02 12:14:58 -0700
committerPalmer Dabbelt <[email protected]>2018-10-22 17:03:36 -0700
commit6db170ff4c088caaf7806c00b29a55f6df07d7b6 (patch)
treed91d87868100acbbf8436728ebcdccc152689766 /drivers/clocksource/riscv_timer.c
parentb18d6f05252d6b3f725c08d8831a46b003df5b6b (diff)
RISC-V: Disable preemption before enabling interrupts
Currently, irq is enabled before preemption disabling happens. If the scheduler fired right here and cpu is scheduled then it may blow up. Signed-off-by: Palmer Dabbelt <[email protected]> [Atish: Commit text and code comment formatting update] Signed-off-by: Atish Patra <[email protected]> Reviewed-by: Christoph Hellwig <[email protected]> Signed-off-by: Palmer Dabbelt <[email protected]>
Diffstat (limited to 'drivers/clocksource/riscv_timer.c')
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