diff options
| author | Stephen Boyd <sboyd@codeaurora.org> | 2017-04-04 15:33:18 -0700 |
|---|---|---|
| committer | Michael Turquette <mturquette@baylibre.com> | 2017-04-12 18:07:37 +0200 |
| commit | 4641d6a560f5088a983a55ea0075e363045631ca (patch) | |
| tree | ff59e25971483d4fdb42d82d9893761308c395a5 /drivers/clk/ti/clkt_dpll.c | |
| parent | b0459491ca2dcda4223b3f3c80a635ae12218580 (diff) | |
| parent | 6c0afb503937a12a8d20a805fcf263e31afa9871 (diff) | |
Merge branch 'for-4.12-ti-clk-cleanups' of https://github.com/t-kristo/linux-pm into clk-next
* 'for-4.12-ti-clk-cleanups' of https://github.com/t-kristo/linux-pm:
clk: ti: convert to use proper register definition for all accesses
clk: ti: dpll44xx: fix clksel register initialization
clk: ti: gate: export gate_clk_ops locally
clk: ti: divider: add driver internal API for parsing divider data
clk: ti: divider: convert TI divider clock to use its own data representation
clk: ti: mux: convert TI mux clock to use its internal data representation
clk: ti: drop unnecessary MEMMAP_ADDRESSING flag
clk: ti: omap4: cleanup unnecessary clock aliases
clk: ti: enforce const types on string arrays
clk: ti: move omap2_init_clk_clkdm under TI clock driver
clk: ti: add clkdm_lookup to the exported functions
clk: ti: use automatic clock alias generation framework
clk: ti: add API for creating aliases automatically for simple clock types
clk: ti: add support for automatic clock alias generation
clk: ti: remove un-used definitions from public clk_hw_omap struct
Diffstat (limited to 'drivers/clk/ti/clkt_dpll.c')
| -rw-r--r-- | drivers/clk/ti/clkt_dpll.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/clk/ti/clkt_dpll.c b/drivers/clk/ti/clkt_dpll.c index b919fdfe8256..ce98da2c10be 100644 --- a/drivers/clk/ti/clkt_dpll.c +++ b/drivers/clk/ti/clkt_dpll.c @@ -213,7 +213,7 @@ u8 omap2_init_dpll_parent(struct clk_hw *hw) if (!dd) return -EINVAL; - v = ti_clk_ll_ops->clk_readl(dd->control_reg); + v = ti_clk_ll_ops->clk_readl(&dd->control_reg); v &= dd->enable_mask; v >>= __ffs(dd->enable_mask); @@ -249,14 +249,14 @@ unsigned long omap2_get_dpll_rate(struct clk_hw_omap *clk) return 0; /* Return bypass rate if DPLL is bypassed */ - v = ti_clk_ll_ops->clk_readl(dd->control_reg); + v = ti_clk_ll_ops->clk_readl(&dd->control_reg); v &= dd->enable_mask; v >>= __ffs(dd->enable_mask); if (_omap2_dpll_is_in_bypass(v)) return clk_hw_get_rate(dd->clk_bypass); - v = ti_clk_ll_ops->clk_readl(dd->mult_div1_reg); + v = ti_clk_ll_ops->clk_readl(&dd->mult_div1_reg); dpll_mult = v & dd->mult_mask; dpll_mult >>= __ffs(dd->mult_mask); dpll_div = v & dd->div1_mask; |