diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2024-07-22 13:50:28 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2024-07-30 10:44:18 +0200 |
| commit | 732a6108ef5eb5fe6b961295d91d80991d724c06 (patch) | |
| tree | f40054287fb9a2948b2e8b69242db8f66adf46fd /drivers/clk/renesas/rcar-gen4-cpg.h | |
| parent | 3284ffb74c75cde0fbad41ab4a7736f56d570bd7 (diff) | |
clk: renesas: rcar-gen4: Add support for fractional 9.24 PLLs
The custom clock driver that models the PLL clocks on R-Car Gen4
supports only fractional 8.25 PLLs, as used on R-Car V4H/V4M.
R-Car S4-8 uses integer and fractional multiplication fields that are
one bit larger resp. smaller, and a slightly different formula.
Extend the existing support to fractional 9.24 PLL, and introduce new
clock types and helper macros to describe these PLLs.
Note that there is no use case for variable fractional 9.24 PLLs yet, as
the Cortex-A55 cores on R-Car S4-8 do not support High Performance mode.
Hence the PLL is always modeled as a fixed PLL, regardless of the
description,
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Link: https://lore.kernel.org/5684eda1260435c8eceabc274e0b18cb280a6341.1721648548.git.geert+renesas@glider.be
Diffstat (limited to 'drivers/clk/renesas/rcar-gen4-cpg.h')
| -rw-r--r-- | drivers/clk/renesas/rcar-gen4-cpg.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/clk/renesas/rcar-gen4-cpg.h b/drivers/clk/renesas/rcar-gen4-cpg.h index 69436309f19d..80a455e62cc1 100644 --- a/drivers/clk/renesas/rcar-gen4-cpg.h +++ b/drivers/clk/renesas/rcar-gen4-cpg.h @@ -21,6 +21,8 @@ enum rcar_gen4_clk_types { CLK_TYPE_GEN4_PLL6, CLK_TYPE_GEN4_PLL_F8_25, /* Fixed fractional 8.25 PLL */ CLK_TYPE_GEN4_PLL_V8_25, /* Variable fractional 8.25 PLL */ + CLK_TYPE_GEN4_PLL_F9_24, /* Fixed fractional 9.24 PLL */ + CLK_TYPE_GEN4_PLL_V9_24, /* Variable fractional 9.24 PLL */ CLK_TYPE_GEN4_SDSRC, CLK_TYPE_GEN4_SDH, CLK_TYPE_GEN4_SD, @@ -55,6 +57,12 @@ enum rcar_gen4_clk_types { #define DEF_GEN4_PLL_V8_25(_name, _idx, _id, _parent) \ DEF_BASE(_name, _id, CLK_TYPE_GEN4_PLL_V8_25, _parent, .offset = _idx) +#define DEF_GEN4_PLL_F9_24(_name, _idx, _id, _parent) \ + DEF_BASE(_name, _id, CLK_TYPE_GEN4_PLL_F9_24, _parent, .offset = _idx) + +#define DEF_GEN4_PLL_V9_24(_name, _idx, _id, _parent) \ + DEF_BASE(_name, _id, CLK_TYPE_GEN4_PLL_V9_24, _parent, .offset = _idx) + #define DEF_GEN4_Z(_name, _id, _type, _parent, _div, _offset) \ DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset) |