diff options
| author | Biju Das <biju.das.jz@bp.renesas.com> | 2022-04-12 17:13:12 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-04-13 12:29:08 +0200 |
| commit | c8b088224c25ef4f5270f9de6a3516181b63f38c (patch) | |
| tree | 96b70a069c80c912b7d1db56bd3e199c06f015dd /drivers/clk/renesas/Makefile | |
| parent | 948f592433f87f8b9c38d43995478eb4561b8629 (diff) | |
clk: renesas: Add support for RZ/G2UL SoC
The clock structure for RZ/G2UL is almost identical to RZ/G2L SoC with
fewer IP blocks. The IP blocks such as WDT1, GPT, H264, GPU and POEG are
not present on RZ/G2UL.
This patch adds minimal clock and reset entries required to boot the
system on Renesas RZ/G2UL SMARC EVK and binds it with the RZ/G2L CPG core
driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20220412161314.13800-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'drivers/clk/renesas/Makefile')
| -rw-r--r-- | drivers/clk/renesas/Makefile | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index d5e571699a30..ca3a9bbcf27a 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -30,6 +30,7 @@ obj-$(CONFIG_CLK_R8A77995) += r8a77995-cpg-mssr.o obj-$(CONFIG_CLK_R8A779A0) += r8a779a0-cpg-mssr.o obj-$(CONFIG_CLK_R8A779F0) += r8a779f0-cpg-mssr.o obj-$(CONFIG_CLK_R9A06G032) += r9a06g032-clocks.o +obj-$(CONFIG_CLK_R9A07G043) += r9a07g043-cpg.o obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o obj-$(CONFIG_CLK_R9A07G054) += r9a07g044-cpg.o obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o |